The power amplifier is one of the most important subsystems of modern communication systems. In the case of satellite downlinks, the power efficiency of high-power amplifiers (HPAs) is important because power requirements directly impact size, weight, and cost of the satellite payload. Because the power efficiency is relatively high when the amplifier is operated near the saturation region, as may be the case for satellite links, the HPA frequently must be operated in such a region. However, the nonlinearity of the amplifier in the near saturation region may introduce considerable distortion in the signal to be amplified. As the output power back off is reduced, the signal to distortion power ratio at the amplifier output is correspondingly reduced. This may place a significant restriction on the amount of back off that needs to be introduced, resulting in a loss of the available output power and, equally important, a reduced power conversion efficiency. This results in an increased demand on D.C. power which, in cases where power is supplied by solar panels, may negatively impact the size, weight, and cost of the satellite payload. Schemes by which the amplifier output back off may be minimized while at the same time mitigating the distortion effects of the amplifier may therefore be desirable. Such mitigation becomes even more important when the amplifier input is comprised of relatively high power signals along with relatively low power signals, as in this case distortion due to the strong signals may result in a very poor signal to distortion power ratio for the weak signals.
Previous techniques to mitigate the amplifier distortion effects generally fall into two categories. In the first category may be techniques that attempt to cancel the nonlinear term arising due to the power amplifier in a feedforward or feedback mode with the compensation operation at radio frequency (RF). The feedforward linearizer consists of two loops. The first loop subtracts samples of the input signal from samples of the amplifier output signal to produce samples of the main amplifier's distortion. The second loop subtracts the amplified sampled distortion from the delayed version of the main amplifier output to obtain the final linearized output. This arrangement is complex to implement, requires a second amplifier that needs to be linear to avoid generating its own distortion terms, and results in power loss due to signal combining at the amplifier output. In the feedback linearizer, the amplifier's input and output are detected and low pass filtered and the resulting baseband signals are compared. The error signal is used to control the gain of the amplifier so as to minimize the distortion. This technique suffers from the bandwidth limitation on the amplifier input signal, as the feedback system may respond to frequencies that are much smaller than the inverse of the delay introduced by the amplifier and associated feedback circuitry; thus, the technique is limited to relatively narrowband signals.
In the predistortion linearization technique, the amplifier input is predistorted such that the overall distortion due to the linearizer and amplifier is minimized. The linearizer gain and phase is obtained iteratively for different input power levels. A digital signal processor (DSP) version of the Cartesian predistortion scheme has been proposed wherein a look up table storing inphase and quadrature components of the linearizer as a function of the input signal envelope is used for predistortion for a set of input signal envelope values. The signal to be amplified is digitized and sampled values of the signal are modified by interpolated value of the stored inphase and quadrature components of the linearizer. The correction is limited by interpolation errors. In a proposed adaptive version of the DSP Cartesian predistortion scheme, the stored values are updated according to the amplifier output signal, which is also limited due to the interpolation errors. Based on the feedback architecture of this scheme, a power amplifier linearizer for a time division duplex system has been proposed wherein a receiving subsystem is shared between the receiver and the power amplifier feedback subsystem, resulting in some reduction of complexity for the time division duplex system.